The present invention relates to integrated circuit design, and more specifically, to merging of storage elements on multi-cycle signal distribution trees into multi-bit cells.
An integrated circuit is comprised of a number of components, such as storage elements (e.g., latches), that are driven by control signals to perform the necessary operations. As the size of an integrated circuit (chip) increases, the distribution of the control signals across the chip may take multiple clock cycles. According to one prior approach, some of the cells (e.g., latches) of a data path are merged into multi-bit latches. These multi-bit cells have a common clock and control lines but individual data input and output pins for each cell. The common clock pin, with the potential internal buffering, reduces the load on the clock distribution network. In addition, the reduced number of pins driven by the clock network due to two or more latches in a common cell reduces the required wiring. As a result, power consumption by the clock distribution network is also reduced.